The proliferation of many new high-speed digital standards is increasingly testing the limits of transmitting a signal. Data must be transmitted with very few bit errors to maintain system reliability. However, system integrity suffers as the risetime of data transitioning from a zero to a one becomes faster. Faster risetimes amplify the effects of poor design of any component found in any physical layer in a system. Faster risetimes mean components must be able to operate at higher frequencies and mitigate frequency dependent effects which are now common in high-speed digital designs. Frequency effects must be considered in designing signal connections.
One often encountered problem is coupling between two signal conductors. Two signal conductors can be electromagnetically coupled by signals carried on each signal conductor. As the signals propagate down the two signal conductors, the signal encounters an impedance due to coupling. If there were no coupling between the signal conductors, the impedance of each signal conductor would be dependent on only the parameters of that particular signal conductor. Further, the impedance of one signal conductor is dependent on the frequency of the signal. However, due to coupling, the impedance on one signal conductor may be dependent on the signal and parameters of an adjacent signal conductor as well as its own signal and parameters. The coupling is also known as crosstalk, which is discussed, for instance, in U.S. Pat. No. 7,108,556.
In some applications, such as printed circuit boards, a trace is used to provide a pathway for signals. The trace (sometimes called a signal trace or wire trace) is generally a conductive pathway (e.g., a line or wire) that allows for electricity to pass from one element to another. The trace that is used to connect conductive vias on either end constitutes what is generally referred to as a “channel” as described in J. Clink and C. Flaherty in “Crosstalk in 10 Gbps Serial Channels: Optimizing the Forgotten Component,” DesignCon 2004, Santa Clara, Calif.; and by J. Clink in “Maximizing 10-Gbps Transmission Path Length in Copper Backplanes With and Without Transceiver Technology,” DesignCon 2003, Santa Clara, Calif.; Vias can extend through the printed circuit board. Adjacent vias can be differential pair plated-through-holes. Adjacent differential pair vias are often routed side-by-side from a source area to a destination area of a printed circuit board or to another printed circuit board thereby interconnecting to a separate printed circuit board. Either side can be considered the destination area or the source area. In either case, between the source area and destination area would be many parallel traces connecting adjacent differential pair channels from one side to the other. On modern printed circuit boards, differential pair traces routed in the same layer are often located within relatively close proximity to one another in a backplane. Some small amount of coupling or crosstalk may be present.
Two differential pairs sufficiently spaced apart will mitigate inter-pair crosstalk, as discussed in “Signal Integrity—Simplified” by E. Bogatin, Prentice-Hall, NL, 2004, pp. 443-444; and “Crosstalk in 10 Gbps Serial Channels: Optimizing the Forgotten Component,” by J. Clink and C. Flaherty, DesignCon 2004, Santa Clara, Calif.;. However, direct electromagnetic coupling between adjacent via pairs will occur and result more severe crosstalk levels.
Adjacent differential pair vias are commonly configured as transmitter pairs routed to the same receiver area of the printed circuit board in a parallel fashion. “Designing 3.125 Gbps Backplane Systems,” Electronica 2002, by G. Patel and K. Ryan, indicates that grouping transmitters and receivers along unshielded adjacent differential pair vias can reduce crosstalk in a printed circuit board channel. This routing method is commonly found in most backplanes where adjacent channels are broken out of the same layer and depth. The purpose of this routing method is primarily to gather signal lines originating from the same source and route them to the same destination, such as signal lines between a silicon device from an exterior daughter card to another daughter card. As indicated by data in the 2004 Clink publication, this grouping strategy is effective for data rates less than 3.125 Gbps, but at higher data rates, the unshielded adjacent differential pair vias create a bottleneck in routers and switches. Side-by-side channel proximity tends to induce accumulated crosstalk between the signal pairs from the source area to the destination area or induce far-end crosstalk or forward crosstalk. Far-end crosstalk is defined as the accumulated crosstalk of coupled signal pairs over a defined distance.
As described in the 2003 Clink publication, there are some commonly practiced techniques employed by backplane designers to mitigate the severity of far-end crosstalk of adjacent channels. For instance, wherever possible, backplane designers attempt to “depopulate” the adjacent channels by assigning those adjacent channels to ground vias. Therefore, for severe crosstalk, the problem can be alleviated by assigning ground vias on every other pair for maximum channel isolation. One via would be assigned as a signal channel, and an adjacent via would be assigned as ground instead of a signal channel. When there is a long row of adjacent pairs, such as in daughter card slots, every other pair would be reassigned as ground vias. The advantage of this arrangement is that the alternating assignment provides a nearly ideal solution for channel isolation. A major disadvantage is that it exponentially reduces the number of available routing pairs in a printed circuit board. To recover the lost routing pairs, the number of signal layers is increased or the area of the printed circuit board panel is increased, resulting in greater overall cost of the printed circuit board. Higher costs may be unacceptable in cost sensitive systems.
Another commonly practiced technique used by backplane designers is described in “Investigating Microvia Technology for 10 Gbps and Higher Telecommunications Systems,” Agilent White Paper—5989-2422EN, by Agilent Technologies, Inc. Agilent Technologies reduces via depths to reduce adjacent via crosstalk by use of short microvias. Vias are connected near the surface of the printed circuit board, instead of within the printed circuit board. Connecting near the surface reduces the via-to-via coupling, thereby minimizing far-end crosstalk. However, one disadvantage is that it is not possible to ideally route all adjacent pairs near the surface of the printed circuit board as the routing space in the layers close the surface are limited. Further, connecting only near the surface provides fewer connection points so that reducing crosstalk by alternating assignments to ground, the method described above, is not feasible.
Another method to mitigate far-end crosstalk is backdrilling, as discussed in “Practical Guidelines for the Implementation of Back Drilling Plated Through Hole Vias in Multi-Gigabit Board Applications,” DesignCon 2003, by Tom Cohen. The DesignCon 2003 conference paper highlights the benefits of backdrilling in printed circuit boards. Backdrilling, also known as counterboring, may be necessary for particular applications, such as when vias are plated-through-holes. Without backdrilling, the unused portion of the plated-through-hole, also known as the resonant stub, acts as a notch filter centered around a frequency primarily determined by the length of the resonant stub. Therefore, as an electrical signal is transitioning through the plated-through-hole, some of the energy of the electrical signal is reflected back to the source because of the resonant stub. To mitigate the effects of the resonant stub, the plated-through-hole is backdrilled. The unused portion of the plated-through-hole is drilled out by boring into the unused portion of the plated-through-hole to remove the electrically conductive material disposed on the surface of the bore.